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1

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

Tzu-Hsuan Hsu, Hang-Ting Lue, Ya-Chin King, Yi-Hsuan Hsiao, Sheng-Chih Lai, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu

Journal:

IEEE Transactions on Electron Devices

Year:

2009

Language:

english

File:

PDF, 1.21 MB

english, 2009

2

[IEEE 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2016.4.25-2016.4.27)] 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Variable-length gateless transistor for analog one-time-programmable memory applications

Cheng, Po-Ruei, Yang, Chih-Sung, Hsu, Meng-Yin, Lin, Chrong Jung, King, Ya-Chin

Year:

2016

Language:

english

File:

PDF, 2.82 MB

english, 2016

3

Punchthrough diode as the transient voltage suppressor for low-voltage electronics

Ya-Chin King, Bin Yu, Pohlman, J., Chenming Hu

Journal:

IEEE Transactions on Electron Devices

Year:

1996

Language:

english

File:

PDF, 364 KB

english, 1996

4

Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies

Chien, Sheng-Yen, Lin, Po-Yen, Chen, Hung-Yu, Lin, Chrong-Jung, King, Ya-Chin

Journal:

IEEE Transactions on Electron Devices

Year:

2014

Language:

english

File:

PDF, 2.12 MB

english, 2014

5

[IEEE 2018 IEEE International Solid - State Circuits Conference - (ISSCC) - San Francisco, CA, USA (2018.2.11-2018.2.15)] 2018 IEEE International Solid - State Circuits Conference - (ISSCC) - A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors

Chen, Wei-Hao, Li, Kai-Xiang, Lin, Wei-Yu, Hsu, Kuo-Hsiang, Li, Pin-Yi, Yang, Cheng-Han, Xue, Cheng-Xin, Yang, En-Yu, Chen, Yen-Kai, Chang, Yun-Sheng, Hsu, Tzu-Hsiang, King, Ya-Chin, Lin, Chorng-Jung,

Year:

2018

Language:

english

File:

PDF, 2.04 MB

english, 2018

6

Gate stress effect on low temperature data retention characteristics of split-gate flash memories

Ling-Chang Hu, An-Chi Kang, Eric Chen, J.R. Shih, Yao-Feng Lin, Kenneth Wu, Ya-Chin King

Journal:

Microelectronics Reliability

Year:

2005

Language:

english

File:

PDF, 380 KB

english, 2005

7

A study of gateless OTP cell using a 45 nm CMOS compatible process

Yi-Hung Tsai, Kai-Chun Lin, Hsin-Yi Chiu, Hung-Sheng Shih, Ya-Chin King, Chrong Jung Lin

Journal:

Solid-State Electronics

Year:

2009

Language:

english

File:

PDF, 822 KB

english, 2009

8

Leakage Suppression of Low-Voltage Transient Voltage Suppressor

Sheng-Huei Dai, Chrong-Jung Lin, Ya-Chin King

Journal:

IEEE Transactions on Electron Devices

Year:

2008

Language:

english

File:

PDF, 233 KB

english, 2008

9

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

Chia-En Huang, Ying-Je Chen, Han-Chao Lai, Ya-Chin King, Chrong Jung Lin

Journal:

IEEE Transactions on Electron Devices

Year:

2009

Language:

english

File:

PDF, 1.30 MB

english, 2009

10

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

Hsien-Chun Chang,, Cheng-Hsiao Lai,, Ya-Chin King,

Journal:

IEEE Sensors Journal

Year:

2003

Language:

english

File:

PDF, 1.32 MB

english, 2003

11

[IEEE 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2014.4.28-2014.4.30)] Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs

Chien, Sheng-Yen, Lin, Po Yen, Hung-Yu Chen,, Chrong Jung Lin,, Ya-Chin King,

Year:

2014

Language:

english

File:

PDF, 938 KB

english, 2014

12

[IEEE 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2014.4.28-2014.4.30)] Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - A high density Twin-Gate OTP cell in pure 28nm CMOS process

Woan Yun Hsiao,, Chin Yu Mei,, Wen Chao Shen,, Tzong Sheng Chang,, Yue Der Chih,, Ya-Chin King,, Chrong Jung Lin,

Year:

2014

Language:

english

File:

PDF, 1.37 MB

english, 2014

13

Charge-based capacitance measurement for bias-dependent capacitance

Yao-Wen Chang,, Hsing-Wen Chang,, Tao-Cheng Lu,, Ya-Chin King,, Wenchi Ting,, Yen-Hui Joseph Ku,, Chih-Yuan Lu,

Journal:

IEEE Electron Device Letters

Year:

2006

Language:

english

File:

PDF, 157 KB

english, 2006

14

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang, Bo-Rong, Meng, Fan-Hsuan, King, Ya-Chin, Lin, Chrong Jung

Journal:

Japanese Journal of Applied Physics

Year:

2017

Language:

english

File:

PDF, 1.79 MB

english, 2017

15

[IEEE 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2018.4.16-2018.4.19)] 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Temperature and stress effect of random telegraph noise in FIND RRAM arrays

Chen, Chin Yuan, Lin, Chrong Jung, King, Ya-Chin

Year:

2018

Language:

english

File:

PDF, 456 KB

english, 2018

16

Embedded 1-Mb ReRAM-Based Computing-in-Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Xue, Cheng-Xin, Chang, Ting-Wei, Chang, Tung-Cheng, Kao, Hui-Yao, Chiu, Yen-Cheng, Lee, Chun-Ying, King, Ya-Chin, Lin, Chrong-Jung, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Chen, Wei-Hao, Ch

Journal:

IEEE Journal of Solid-State Circuits

Year:

2019

Language:

english

File:

PDF, 7.63 MB

english, 2019

17

Embedded 1-Mb ReRAM-Based Computing-in-Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Xue, Cheng-Xin, Chang, Ting-Wei, Chang, Tung-Cheng, Kao, Hui-Yao, Chiu, Yen-Cheng, Lee, Chun-Ying, King, Ya-Chin, Lin, Chrong-Jung, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Chen, Wei-Hao, Ch

Journal:

IEEE Journal of Solid-State Circuits

Year:

2019

File:

PDF, 7.63 MB

2019

18

Band-to-band tunneling induced substrate hot electron injection (BBISHE) to perform programming for NOR flash memory

Meng-Yi Wu, Sheng-Huei Dai, Kung-Hong Lee, Shu-Fen Hu, Ya-Chin King

Journal:

Solid-State Electronics

Year:

2006

Language:

english

File:

PDF, 297 KB

english, 2006

19

Self-convergent scheme for logic-process-based multilevel/analog memory

Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King

Journal:

IEEE Transactions on Electron Devices

Year:

2005

Language:

english

File:

PDF, 627 KB

english, 2005

20

A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

Yuan Heng Tseng, Chia-En Huang, Kuo, C., Chih, Y., Ya-Chin King, Chrong Jung Lin

Journal:

IEEE Transactions on Electron Devices

Year:

2011

Language:

english

File:

PDF, 946 KB

english, 2011

21

Three-Dimensional ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process

Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, Chrong Jung Lin, Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Chen, F.T., Ming-Jinn Tsai

Journal:

IEEE Transactions on Electron Devices

Year:

2011

Language:

english

File:

PDF, 1.52 MB

english, 2011

22

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Chang, Meng-Fan, Shen, Shin-Jang, Liu, Chia-Chi, Wu, Che-Wei, Lin, Yu-Fan, King, Ya-Chin, Lin, Chorng-Jung, Liao, Hung-Jen, Chih, Yu-Der, Yamauchi, Hiroyuki

Journal:

IEEE Journal of Solid-State Circuits

Year:

2013

Language:

english

File:

PDF, 3.01 MB

english, 2013

23

[IEEE 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design - Opio, France (2008.05.18-2008.05.22)] 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design - A Study of Sub-40nm FinFET BE-SONOS NAND Flash

Hsu, Tzu-Hsuan, Lue, Hang-Ting, Peng, Wu-Chin, Tsai, Cheng-Hung, King, Ya-Chin, Wang, Szu-Yu, Wu, Ming-Tsung, Hong, Shih-Ping, Hsieh, Jung-Yu, Yang, Ling-Wu, Lian, Nan-Tzu, Yang, Tahone, Chen, Kuang-C

Year:

2008

Language:

english

File:

PDF, 796 KB

english, 2008

24

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

Meng-Fan Chang,, Che-Wei Wu,, Chia-Cheng Kuo,, Shin-Jang Shen,, Sue-Meng Yang,, Ku-Feng Lin,, Wen-Chao Shen,, Ya-Chin King,, Chorng-Jung Lin,, Yu-Der Chih,

Journal:

IEEE Journal of Solid-State Circuits

Year:

2013

Language:

english

File:

PDF, 2.51 MB

english, 2013

25

[IEEE 2014 IEEE International Solid- State Circuits Conference (ISSCC) - San Francisco, CA, USA (2014.02.9-2014.02.13)] 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) - 19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Chang, Meng-Fan, Wu, Jui-Jen, Chien, Tun-Fei, Liu, Yen-Chen, Yang, Ting-Chin, Shen, Wen-Chao, King, Ya-Chin, Lin, Chorng-Jung, Lin, Ku-Feng, Chih, Yu-Der, Natarajan, Sreedhar, Chang, Jonathan

Year:

2014

Language:

english

File:

PDF, 2.64 MB

english, 2014

26

A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation

. Cheng-hsiao Lai, . Ya-chin King, . Shi-yu Huang

Journal:

IEEE Sensors Journal

Year:

2006

Language:

english

File:

PDF, 620 KB

english, 2006

27

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

Te-liang Lee, Yi-hung Tsai, Wun-jie Lin, Hsiao-lan Yang, Chiu-wang Lien, Chrong Jung Lin, Ya-chin King

Journal:

IEEE Electron Device Letters

Year:

2011

Language:

english

File:

PDF, 223 KB

english, 2011

28

Comments on "Jamming Susceptibility"

Huang, Chia-En, Chen, Hsin-Ming, Lai, Han-Chao, Chen, Ying-Je, King, Ya-Chin, Lin, Chrong Jung

Journal:

IEEE Transactions on Aerospace and Electronic Systems

Year:

1969

Language:

english

File:

PDF, 450 KB

english, 1969

29

Built-In Self-Repair for Die-to-Die Misalignment of Multidie Space Sensors

Chen, Chun-Fu, Huang, Shi-Yu, King, Ya-Chin

Journal:

IEEE Sensors Journal

Year:

2007

Language:

english

File:

PDF, 262 KB

english, 2007

30

[IEEE IEEE International SOC Conference - Portland, OR, USA (17-20 Sept. 2003)] IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. - A high dynamic range CMOS image sensor design based on two-frame composition

Bo-Rong Lin,, Shi-Yu Huang,, Cheng-Hsiao Lai,, Ya-Chin King,

Year:

2003

Language:

english

File:

PDF, 320 KB

english, 2003

31

[IEEE Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan (June 3-5, 1997)] Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - AC Charge Centroid Model For Quantization Of Inversion Layer In N-MOSFET

Ya-Chin King,, Fujioka, H., Kamohara, S., Wen-Chin Lee,, Chenming Hu,

Year:

1997

Language:

english

File:

PDF, 377 KB

english, 1997

32

[IEEE 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual - Phoenix, AZ, USA (2007.04.15-2007.04.19)] 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual - Leakage Suppression of Low Voltage Transient Voltage Suppressor

Dai, Sheng-Huei, Wang, Hai-Ning, Chiang, Ming-Tai, Lin, Chrong-Jung, King, Ya-Chin

Year:

2007

Language:

english

File:

PDF, 251 KB

english, 2007

33

[IEEE 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2013.04.22-2013.04.24)] 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - 28nm high-k metal gate RRAM with fully compatible CMOS logic processes

Chin Yu Mei,, Wen Chao Shen,, Chih, Y -D., Ya-Chin King,, Chrong Jung Lin,

Year:

2013

File:

PDF, 839 KB

2013

34

Efficient Low-Temperature Data Retention Lifetime Prediction for Split-Gate Flash Memories Using a Voltage Acceleration Methodology

Hu, Ling-Chang, Kang, An-Chi, Wu, Tai-Yi, Shih, J. R., Lin, Yao-Feng, Wu, Kenneth, King, Ya-Chin

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2006

Language:

english

File:

PDF, 809 KB

english, 2006

35

Punchthrough transient voltage suppressor for low-voltage electronics

Ya-Chin King,, Bin Yu,, Pohlman, J., Chenming Hu,

Journal:

IEEE Electron Device Letters

Year:

1995

Language:

english

File:

PDF, 216 KB

english, 1995

36

[IEEE 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) - Taipei, Taiwan (03-05 Aug. 2005)] 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) - Novel Self-Convergent Scheme Logic-Process-Based Multilevel/Analog EEPROM Memory

Kung-Hong Lee,, Shih-Chen Wang,, Ya-Chin King,

Year:

2005

Language:

english

File:

PDF, 186 KB

english, 2005

37

A Resist-Protection-Oxide Transistor With Adaptable Low-Frequency Noise for Stochastic Neuromorphic Computation in VLSI

Chiu, Tang-Jung, King, Ya-Chin, Gong, Jeng, Tsai, Yi-Hung, Chen, Hsin

Journal:

IEEE Electron Device Letters

Year:

2011

Language:

english

File:

PDF, 238 KB

english, 2011

38

A New Sensing Scheme for Sensitivity Enhancement of Low-Temperature Polycrystalline Silicon Photodetecors

Chen, Chih-Yang, Lin, Chrong-Jung, King, Ya-Chin

Journal:

IEEE Sensors Journal

Year:

2011

Language:

english

File:

PDF, 1.36 MB

english, 2011

39

A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate

Yi-Hung Tsai,, Kai-Chun Lin,, Cheng-Hsiung Kuo,, Yue-Der Chih,, Chrong-Jung Lin,, Ya-Chin King,

Journal:

IEEE Electron Device Letters

Year:

2009

Language:

english

File:

PDF, 325 KB

english, 2009

40

28-nm 2T High-$K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Mei, Chin Yu, Shen, Wen Chao, Wu, Chun Hsiung, Chih, Yue-Der, King, Ya-Chin, Lin, Chrong Jung, Tsai, Ming-Jinn, Tsai, Kan-Hsueh, Chen, Frederick T.

Journal:

IEEE Electron Device Letters

Year:

2013

Language:

english

File:

PDF, 532 KB

english, 2013

41

[IEEE 2012 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu (2012.04.23-2012.04.25)] Proceedings of Technical Program of 2012 VLSI Technology, System and Application - 32nm strained nitride MTP cell by fully CMOS logic compatible process

Wen Chao Shen,, Chia-En Huang,, Hsun OuYang,, Ya-Chin King,, Chrong Jung Lin,

Year:

2012

Language:

english

File:

PDF, 522 KB

english, 2012

42

[IEEE 2010 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2010.12.6-2010.12.8)] 2010 International Electron Devices Meeting - Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process

Ching-Hua Wang,, Yi-Hung Tsai,, Kai-Chun Lin,, Meng-Fan Chang,, Ya-Chin King,, Chrong-Jung Lin,, Shyh-Shyuan Sheu,, Chen, Yu-Sheng, Lee, Heng-Yuan, Chen, Frederick T., Ming-Jinn Tsai,

Year:

2010

Language:

english

File:

PDF, 433 KB

english, 2010

43

[IEEE 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) - Ishigaki, Japan (2014.11.17-2014.11.20)] 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) - A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips

Chang, Meng-Fan, Wu, Che-Wei, Hung, Jui-Yu, King, Ya-Chin, Lin, Chomg-Jung, Ho, Mon-Shu, Kuo, Chia-Cheng, Sheu, Shyh-Shyuan

Year:

2014

Language:

english

File:

PDF, 305 KB

english, 2014

44

A new laterally conductive bridge random access memory by fully CMOS logic compatible process

Hsieh, Min-Che, Chin, Yung-Wen, Lin, Yu-Cheng, Chih, Yu-Der, Tsai, Kan-Hsueh, Tsai, Ming-Jinn, King, Ya-Chin, Lin, Chrong Jung

Journal:

Japanese Journal of Applied Physics

Year:

2014

Language:

english

File:

PDF, 819 KB

english, 2014

45

A new 28 nm high- k metal gate CMOS logic one-time programmable memory cell

Hsiao, Woan Yun, Mei, Chin Yu, Shen, Wen Chao, Chih, Yue Der, King, Ya-Chin, Lin, Chrong Jung

Journal:

Japanese Journal of Applied Physics

Year:

2014

Language:

english

File:

PDF, 597 KB

english, 2014

46

A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process

Hsiao, Woan Yun, Peng, Ping Chun, Chang, Tzong-Sheng, Chih, Yu-Der, Tsai, Wu-Chin, Chang, Meng-Fan, Chien, Tun-Fei, King, Ya-Chin, Lin, Chrong-Jung

Journal:

IEEE Transactions on Electron Devices

Year:

2015

Language:

english

File:

PDF, 2.81 MB

english, 2015

47

High-Density FinFET One-Time Programmable Memory Cell With Intra-Fin-Cell-Isolation Technology

Peng, Ping Chun, Chen, Yu-Zheng, Hsiao, Woan Yun, Chen, Kuang-Hsin, Lin, Ching-Pin, Tien, Bor-Zen, Chang, Tzong-Sheng, Lin, Chrong Jung, King, Ya-Chin

Journal:

IEEE Electron Device Letters

Year:

2015

Language:

english

File:

PDF, 618 KB

english, 2015

48

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Yeh, Teng-Hao, Wu, Chen-Jun, Hu, Chih-Wei, Chen, Wei-Chen, Lue, Hang-Ting, Shih, Yen-Hao, King, Ya-Chin, Lu, Chih-Yuan

Journal:

IEEE Electron Device Letters

Year:

2015

Language:

english

File:

PDF, 961 KB

english, 2015

49

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Yeh, Teng-Hao Elton, Chen, Wei-Chen, Hsu, Tzu-Hsuan Bruce, Du, Pei-Ying Penny, Hsieh, Chih-Chang, Lue, Hang-Ting, Shih, Yen-Hao, King, Ya-Chin, Lu, Chih-Yuan

Journal:

IEEE Transactions on Electron Devices

Year:

2016

Language:

english

File:

PDF, 3.14 MB

english, 2016

50

Investigation of Set/Reset Operations in CMOS Logic-Compatible Contact Backfilled RRAMs

Chen, Hung-Yu, Chen, Hsien Hao, King, Ya-Chin, Lin, Chrong-Jung

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2016

Language:

english

File:

PDF, 838 KB

english, 2016